For an integrated circuit to function properly, it is necessary that the data loaded into a memory is not corrupted. One type of integrated circuit which relies on data loaded into memory elements is a programmable logic device (PLD). A PLD is designed to be user-programmable so that users may implement logic designs of their choice. Programmable logic circuits of a PLD comprise gates which are configurable by a user of the circuit to implement a specific circuit design. One type of PLD is the Complex Programmable Logic Device, or CPLD. A CPLD includes two or more “function blocks” connected together and to input/output (I/O) resources by an interconnect switch matrix. Each function block of the CPLD includes a two-level AND/OR structure similar to that used in a Programmable Logic Array (PLA) or a Programmable Array Logic (PAL) device. In some CPLDs, configuration data is stored on-chip in non-volatile memory, then downloaded to volatile memory as part of an initial configuration sequence. Another type of PLD is a field programmable gate array (FPGA). In a typical FPGA, an array of configurable logic blocks (CLBs) is coupled to programmable input/output blocks (IOBs). The CLBs and IOBs are interconnected by a hierarchy of programmable routing resources. These CLBs, IOBs, and programmable routing resources are customized by loading a configuration bitstream, typically from off-chip memory, into configuration memory cells of the FPGA. For both of these types of programmable logic devices, the functionality of the device is controlled by configuration data bits of a configuration bitstream provided to the device for that purpose.
PLDs also have different “modes” depending on the operations being performed on them. A specific protocol allows a programmable logic device to enter into the appropriate mode. Typical PLDs have internal blocks of configuration memory which specify how each of the programmable cells will emulate the user's logic. During a “program” mode, a configuration bitstream is provided to non-volatile memory, such as a read-only memory (ROM) (e.g., a programmable ROM (PROM), an erasable PROM (EPROM), or an electrically erasable PROM (EEPROM)) either external or internal to the programmable logic device. Each address is typically accessed by specifying its row and column addresses. During system power up of a “startup” mode, the configuration bits are successively loaded from the non-volatile memory into static random access memory (SRAM) configuration latches of a configuration logic block.
Certain applications of programmable logic devices, such as military, aerospace, and high-reliability communications, must be able to operate reliably in environments subjected to various radiation effects caused by energetic heavy ions and subatomic particles striking the silicon. When an ion strikes a circuit, it may cause a glitch in voltage at a node which results in an unintentional state change in a data storage node. This type of error is commonly known as a soft error. Because it is highly unlikely that more than one ion will strike the circuit simultaneously, it is only necessary to consider one ion strike leading to a single-event effect (SEE). Two of the most common single-event effects are single-event upsets (SEU), which refer to the loss of data in a storage element caused by an ion striking the storage element directly, and single-event transients (SET), which refer to the loss of data caused by a glitch on the clock or other input signals as a result of an ion strike, changing the internal node voltages of the circuit for a short time interval. As a result, information stored in memory cells, latches and flip-flops might be lost, causing incorrect system operation.
System level solutions, such as error detection and correction or triple modular redundancy (TMR), are available to provide SEU and SET tolerance. TMR is a technique for ensuring that a circuit functions even if one part of the circuit is not operating properly, where a majority vote will ensure that the output of the circuit is correct even when one copy of the circuit fails. For example, if an SEU or SET upsets a state machine, the state machine will resynchronize with its redundant partners while the whole TMR system still generates correct outputs. Therefore, state logic may operate uninterrupted in the presence of SEUs and SETS. However, implementing a circuit in triple modular redundancy may be a costly and difficult task.
There are also design techniques that may be applied at circuit level to prevent storage elements from being affected by an SEU, to enhance the system level soft-error tolerant solution. To prevent an SEU, a dual interlocked storage cell (DICE), which is described by Calin, Nicolaidis and Velazco in “Upset Hardened Memory Design for Submicron CMOS Technology” (IEEE Trans. On Nuclear Science, Vol. 43, No. 6, December 1996), may be used. When an SEU strike hits and disturbs the voltage on one of the internal nodes of the dual interlocked storage cell, the circuit will return to its previous state after the SEU generated charge has been collected and dissipated. Therefore, disturbing only one data storage node will not change the stored data. However, a dual interlocked storage cell does not prevent storage elements from being affected by SET upsets.
Accordingly, there is a need for an improved latch and method of preventing an unintentional state change in a data storage node of a latch.